After successful eFPGA CDR and its data package delivery, the eFPGA embedding an adder function passed its first RTL simulation in PROMISE Pilot Circuit. This first simulation paves the way for the Front-end design activities finalization.
Imec announce the achievement of CDR completion for the embedded NVM IP. The IP is effectively designed from scratch... read more
ISD announces the completion of the DAC IP. This is a single channel, low-noise, radiation hardened DAC adequate for... read more
ISD announces the 500mA - 1.8V LDO design completion; it is a key block that will deliver supply to... read more
IMEC can announce the successful completion of its DARE radiation hardened LVDS IO simulated up to 720MHz as part... read more
The consortium announces Fab-Out of the PROMISE Pilot Circuit read more
IT announces the completion of the BGR IP. The radiation hardened BGR is designed for reliable performance in space... read more
IT announces the completion of the LO IP. The LO presents a 16MHz on-chip oscillator based on a frequency-locked... read more
VTT announces the completion of the radiation hardened POR IP. This low power (<300μA) supervisory circuit monitors up to... read more
After a first successful phase of collaboration with IMEC, that led to a set of optimized radiation hardened standard... read more
ISD announces the completion of the PLL IP. An associative block that enables the PLL to operate with a reference... read more
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