Imec announce the achievement of CDR completion for the embedded NVM IP. The IP is effectively designed from scratch using SONOS embedded Non-Volatile Memory. The NVM is a highly sophisticated IP containing numerous innovations at several levels of the design. Data integrity is a key goal of the design....
VTT announces the completion of the radiation hardened POR IP. This low power (<300μA) supervisory circuit monitors up to two power supply voltages, 1.8V/3.3V and takes appropriate actions if a voltage goes out of boundaries. When rising power supply voltage reaches a sufficient level, POR creates 100μs delay before...
ISD announces the completion of the ADC IP. This is 6 multiplexed input (differential or single-ended), low-noise, radiation hardened ADC adequate for sampling signals ranging from DC to 40kHz. The ADC converts the input voltage into a 24-bit word using an SPI - like serial interface. The system architecture...
ISD announces the completion of the DAC IP. This is a single channel, low-noise, radiation hardened DAC adequate for converting digital signals ranging from DC to 50kHz. The DAC receives 24-bit input data in a synchronous serial format and converts it into a differential current analogue output signal. The...
IT announces the completion of the BGR IP. The radiation hardened BGR is designed for reliable performance in space application while considering process, voltage, and temperature variations and the impact of single-event transients and total ionizing dose. A worst-case temperature coefficient better than 6.13 ppm/°C, over an extreme temperature...
IT announces the completion of the LO IP. The LO presents a 16MHz on-chip oscillator based on a frequency-locked loop (FLL) which is radiation hardened by design and intended for space applications. The oscillator maintains a temperature stability lower than 50ppm/ºC over process, voltage and temperature variations and low...
ISD announces the completion of the PLL IP. An associative block that enables the PLL to operate with a reference clock from multiple sources (Crystal Oscillator, digital clock or sine wave) and a CMOS Output buffer that will enrich the existing DARE180XH_IO library are included in the CDR data package....
IMEC can announce the successful completion of its DARE radiation hardened LVDS IO simulated up to 720MHz as part of its contribution to the PROMISE project.
ISD announces the 500mA - 1.8V LDO design completion; it is a key block that will deliver supply to any digital core using PROMISE library. After delivery of the data-package it passed successfully the CDR milestone.
After a first successful phase of collaboration with IMEC, that led to a set of optimized radiation hardened standard cells for best PPAs (Power, Performances, Area) covered in task 2.1 of WP2, Menta has successfully delivered on schedule to the PROMISE project, its radiation hardened embedded FPGA (eFPGA) IP...
