ISD announces the completion of the PLL IP. An associative block that enables the PLL to operate with a reference clock from multiple sources (Crystal Oscillator, digital clock or sine wave) and a CMOS Output buffer that will enrich the existing DARE180XH_IO library are included in the CDR data package....
IMEC can announce the successful completion of its DARE radiation hardened LVDS IO simulated up to 720MHz as part of its contribution to the PROMISE project.
ISD announces the 500mA - 1.8V LDO design completion; it is a key block that will deliver supply to any digital core using PROMISE library. After delivery of the data-package it passed successfully the CDR milestone.
After a first successful phase of collaboration with IMEC, that led to a set of optimized radiation hardened standard cells for best PPAs (Power, Performances, Area) covered in task 2.1 of WP2, Menta has successfully delivered on schedule to the PROMISE project, its radiation hardened embedded FPGA (eFPGA) IP...
After successful eFPGA CDR and its data package delivery, the eFPGA embedding an adder function passed its first RTL simulation in PROMISE Pilot Circuit. This first simulation paves the way for the Front-end design activities finalization.
After a first successful phase of collaboration with IMEC, that led to a set of optimized radiation hardened standard cells for best PPAs (Power, Performances, Area) covered in task 2.1 of WP2, Menta has successfully delivered on schedule to the PROMISE project, its radiation hardened embedded FPGA (eFPGA) IP...
