ISD announces the completion of the DAC IP. This is a single channel, low-noise, radiation hardened DAC adequate for converting digital signals ranging from DC to 50kHz. The DAC receives 24-bit input data in a synchronous serial format and converts it into a differential current analogue output signal. The converter uses a third-order multi-bit Sigma-Delta modulator.
After a first successful phase of collaboration with IMEC, that led to a set of optimized radiation hardened standard... read more
IT announces the completion of the LO IP. The LO presents a 16MHz on-chip oscillator based on a frequency-locked... read more
ISD announces the completion of the ADC IP. This is 6 multiplexed input (differential or single-ended), low-noise, radiation hardened... read more
PROMISE consortium announces the achievement of CDR completion for the PROMISE Pilot Circuit on 31st of January 2023. read more
The consortium announces Fab-Out of the PROMISE Pilot Circuit read more
ISD announces the 500mA - 1.8V LDO design completion; it is a key block that will deliver supply to... read more
ISD announces the completion of the PLL IP. An associative block that enables the PLL to operate with a reference... read more
After successful eFPGA CDR and its data package delivery, the eFPGA embedding an adder function passed its first RTL... read more
IMEC can announce the successful completion of its DARE radiation hardened LVDS IO simulated up to 720MHz as part... read more
After a first successful phase of collaboration with IMEC, that led to a set of optimized radiation hardened standard... read more
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