PROMISE LVDS IP CDR Milestone successfully reached
IMEC can announce the successful completion of its DARE radiation hardened LVDS IO simulated up to 720MHz as part of its contribution to the PROMISE project.
PROMISE 1.8V LDO regulator IP CDR Milestone successfully reached
ISD announces the 500mA - 1.8V LDO design completion; it is a key block that will deliver supply to any digital core using PROMISE library. After delivery of the data-package it passed successfully the CDR milestone.
PROMISE core standard cells, level shifters, IOs and IO/POC IP CDR Milestone successfully reached
After a first successful phase of collaboration with IMEC, that led to a set of optimized radiation hardened standard cells for best PPAs (Power, Performances, Area) covered in task 2.1 of WP2, Menta has successfully delivered on schedule to the PROMISE project, its radiation hardened embedded FPGA (eFPGA) IP...
PROMISE Pilot Circuit – eFPGA integration successful!
After successful eFPGA CDR and its data package delivery, the eFPGA embedding an adder function passed its first RTL simulation in PROMISE Pilot Circuit. This first simulation paves the way for the Front-end design activities finalization.
PROMISE eFPGA IP CDR Milestone successfully reached – the first critical enabler for ASSP
After a first successful phase of collaboration with IMEC, that led to a set of optimized radiation hardened standard cells for best PPAs (Power, Performances, Area) covered in task 2.1 of WP2, Menta has successfully delivered on schedule to the PROMISE project, its radiation hardened embedded FPGA (eFPGA) IP...
