A joint venture between Thales (67%) and Leonardo (33%), Thales Alenia Space is a key supplier of satellite and orbital infrastructure solutions. The company develops the very latest space and ground segment for scientific, commercial, military and security applications. It is a global market leader in telecommunications, navigation, space exploration and earth observation, particularly for weather forecasting, altimetry, oceanography and environmental management applications. The Company which achieved revenues of 2,6 billion euros in 2017, has a total of 8000 employees located in 17 industrial sites in nine countries.
Role in the project
THALES ALENIA SPACE – France will play 4 roles in PROMISE :
- TASF will coordinate the technical activities in PROMISE project. Accordingly, TASF will take charge to guarantee the consistency of all the technical activities from design to manufacturing, tests and qualification to ensure the overall final compliance of the Pilot Circuit and embedded IPs with their related specification.
- As hardened design expert, in WP1, TASF will establish standards for Mixed Signal IP Cores design (including hardening recommendation) and will contribute to IP interface standard and usage definition.
- As an expert in mixed-signal ASIC supply chain management, TASF will lead the WP3 to define manufacturing and qualification standards, identify the European actors and select the Pilot Circuit supply chain.
- As end-user, TASF will lead in WP1 the PROMISE’IPs specification as well as the Pilot Circuit specification. In WP2, TASF will also design the Pilot Circuit front-end, contributing to the overall PROMISE design process validation. Finally, in WP4 and 5, TASF will manage the selected supply chain to manufacture and qualify the Pilot Circuit silicon.
Significant infrastructure and/or any major items of technical equipment, relevant to the proposed work
The Thales Alenia Space Toulouse ASIC and FPGA design center is the major and most experienced design center of Thales Alenia Space. It is composed of twenty-five experienced design engineers with a qualified engineer diploma in electrical engineering and benefits from the system skills of the Power and Processing Product Line. On the hardware aspects, all the designers have their own HP Linux workstation (8 to 20 cores processor) with at least 32GB of RAM (up to 128GB) connected to a 100Mbps network. Regarding the software aspects, a complete design entry solution is available with:
- HDL Designer (Mentor) for VHDL coding
- CatapultC (Mentor) for architectural synthesis
- Questasim (Mentor) for digital and mixed simulation
- Veloce 2 (Mentor) for hardware accelerated simulation
- DC-Compiler (Synopsys) for digital synthesis
- Test Compiler (Synopsys) for DFT insertion
- Tetramax (Synopsus) for pattern generation
- Formality (Synopsys) for formal proof
- Primetime (Synopsys) for static timing analysis
- Virtuoso Suite (Cadence) for analog full custom schematic and layout
- ADE-L (Cadence) and Eldo (Mentor) for analog and mixed simulation environment
- Calibre (Mentor) and Assura (Cadence) for extraction, DRC and LVS
Linked projects and initiatives
- CNES / PLEIADES : TAS-F has designed 3 ASIC in STMicroelectronics 1.2µm BiCMOS hardened technology. The 3 ASIC have been supplied by SERMA (France). Test and HTOL qualification were performed by FABLESS (Bulgaria). TAS-F has set up successfully this supply chain having a European footprint on a project-based approach.
- ESA HIVAC/VASP ASIC contract : the VASP ASIC has been designed and hardened by TAS-F and a Portuguese partner (CHIPIDEA, now SYNOPSYS) in a XFAB commercial 350nm technology using a TAS-F proprietary hardened digital library and RHBD approach for analog cells. It is successfully qualified and is embedded is several satellite programs : for TESAT, MTG, IASI-NG MVU, SENTINEL 4, PLATO. TAS-F has set up a supply chain for analog and mixed ASICs on a project-based approach, and several other circuits were qualified. TAS-F can therefore efficiently coordinate PROMISE’s supply chain activities and define & share a standard plan for manufacturing and qualification.
- FLIP, co-founded by CNES : OPAL ASIC has been developed to improve competitiveness of LDLA15 and LDRIVER equipment. It has been designed in XFAB 350nm technology. It is successfully qualified, manufactured through our mixed ASIC supply Chain and is embedded is several satellite programs : in flight with BANGABANDHU 1 since March 2018, and to be launched with EG1, Yamal 601, GX5, BB4A, EXPRESS 80-103, SES17, AMU 3-7, KONNECT, Loutch 5M. TAS-F is mastering design methodology & hardening and can therefore efficiently coordinate technical design activities and support the IPs hardening to reduce the technical risks.
- RXNEO, co-founded by CNES : ASIC MIGAL mixed & HV 6V5 circuit, is the first mixed ASIC for digital RF items configuration and DC voltage analog regulation functions. It provides improvement for cost, performances and delivery lead time. It including test structure up to 15V. It will be embedded in next telecom receiver product. Prototypes are manufactured and under test compliance ; manufacturing of flight models is on-going.
- ESA/KIPSAT STMicroelectronics 65nm radhard technology development ; TAS-F contributed to standard cells and IPs (PLL, HSSL) specification. CNES/CETO : TAS-F was responsible of the Pilot Circuit design. The objective was to validate the design and supply chain capability. The Pilot Circuit is now the SEC for the qualified perimeter of the technology and supply chain by MICROCHIP.